1. Field of the Invention
The present invention relates to A/D converters for converting analogue signals into digital signals, and more particularly, to a parallel comparison type A/D converter providing a digital signal by bilevel-processing (thresholding) parallelly an analogue signal with a plurality of reference potentials.
2. Description of the Background Art
By virtue of easiness in removing noise, processing signals, designing circuits and supporting high level functions, digital signal processing is carried out widely not only in the technical field of computers, but also in fields in which signal processing was carried out analoguely in the past. Digital signal processing requires conversion of analogue signals into digital signals. To this end, A/D converters are used.
FIG. 1 is a schematic diagram of a structure of a conventional A/D converter. The A/D converter of FIG. 1 converts an input analogue signal into a 4-bit digital signal. Such an A/D converter is disclosed in an article entitled "A10-bit 5-M sample/s CMOS Two-step Flash ADC" by J. Doernberg et al. in JSSC Vol. 24, No. 2, pp. 241-249, issued April, 1989.
Referring to FIG. 1, a conventional A/D converter comprises a resistor voltage divider 1 for generating a plurality of reference potentials, a comparator group 2 for bilevel-processing an input analogue voltage signal received from a node 6 by the reference potentials from resistor voltage divider 1 and providing this processing result parallelly, and an encoder 3 for encoding the output signal from comparator group 2 to provide a digital signal.
Resistor voltage divider 1 comprises a plurality of resistors R0 - R3 (four resistors in FIG. 1) connected in series between a reference voltage applying terminal 4 supplied with a first reference potential and a reference voltage applying terminal 5 supplied with a second reference voltage. Each of resistors R0-R3 have the same resistance r. The interconnection nodes of reference voltage applying terminals 4, 5 and resistors R0-R3 are coupled to the inputs of comparator group 2 as reference voltage output terminals N0-N4.
The first reference voltage applying terminal 4 receives a first reference voltage Vref. The second reference voltage applying terminal 5 receives a second reference voltage 0V. 0, Vref/4, Vref/2, 3.Vref/4 and Vref are provided as reference voltages from output nodes N0-N4
Comparator group 2 comprises a plurality of comparators each receiving a predetermined set of reference voltages applied from reference voltage output terminals N0-N4 and an analogue voltage signal applied to terminal 6 receiving a to-be-compared voltage for bilevel-processing. Because the resolution of the A/D converter of FIG. 1 is 4 bits (the output of encoder 3 is of 4 bits), the number of comparators included in comparator group 2 is 2.sup.4 -1=15.
Encoder 3 comprises an AND gate array 3a detecting the boundary between "0" and "1" of the data of 15 bits provided from comparator group 2, and a ROM 3b providing a digital value by encoding the 15-bit data into a 4-bit data using the output from AND gate array 3a as an address signal.
FIG. 2 shows a specific structure of AND gate array 3a and ROM 3b. Referring to FIG. 2, AND gate array 3a comprises sixteen NAND gates G10-G115 that is one more in number than the comparators (15; #1-#15) in comparator group 2. NAND gate Glj (j=1-14) has one input coupled to receive the output of comparator #j-1, and the other input coupled to receive the output of inverter G2j. Inverter G2j receives the output of comparator #j. NAND gate G10 has one input receiving supply potential V.sub.cc and the other input receiving the output of inverter G20. NAND gate G115 has one input receiving the output of comparator #14 and the other input receiving the supply potential V.sub.cc.
AND gate array 3a further comprises an inverter G3i receiving the output of NAND gate Gli (i =0-14). NAND gate Gli and inverter G3i form an AND gate.
The gate circuit constituted by NAND gate Glj and inverter G2j provide a complementary signal to an output of the AND gate. The output of NAND gate G10 is applied to ROM 3b via inverter G30. The output of NAND gate G115 is applied directly to ROM 3b.
ROM 3b compresses the 16-bit data (assuming that complementary data is 1 bit) from AND gate array 3a into data of 4 bits B3-B0. ROM 3b comprises 16 rows of transistors provided corresponding to the 16 NAND gates. Each transistor row comprises a P channel MOS transistor QP and an N channel MOS transistor QN. Transistor QP transmits an "H" signal of supplied potential V.sub.cc level to a related data line (B0-B3). Transistor QN transmits "L" signal of ground potential V.sub.ss level to a related data line (B0-B3). The gate of transistor QP receives the output of a corresponding NAND gate of AND gate array 3a. The gate of transistor QN receives the output of a corresponding inverter of AND gate array 3a. Each transistor row comprises PMOS transistors QP and NMOS transistors QN arranged to represent in binary notation the reference number j (decimal) of a corresponding NAND gate Glj.
For example, when an output of comparators #14 - #0 is (00 . . . 0111), only the output of NAND gate G13 is L. At this condition, data (B3, B2, B1, B0) =(0011) is provided from ROM 3b. When outputs of comparators #14 #0 are all H, only the output of NAND gate G115 is L, and data of (1111) is provided from ROM b. When all the outputs of comparators #14 - #0 are L, only the output of NAND gate G10 is L, and data of (0000) is provided from ROM 3b.
FIG. 3 shows the structure of the comparators in comparator group 2. Referring to FIG. 3, the comparator comprises four coupling capacitors C0-C3 each having equal capacitance, and an inverting amplifier 11. One node of each of coupling capacitors C0-C3 is connected to input nodes 7-10 or analogue voltage applying terminal 6 via switches S0-S3, respectively. The other nodes of coupling capacitors C0-C3 are connected in common to the inverting amplifier 11. The input of inverting amplifier 11 is also connected to bias voltage applying terminal 12 via switch S4.
The comparator group 2 of FIG. 1 is provided with fifteen comparators each having a structure shown in FIG. 3. Except for the difference in voltages applied to reference voltage applying terminals 7-10, the fifteen comparators each have a similar structure.
FIG. 4 shows, in a list, the connection relation between reference voltage applying terminals 7-10 of each comparator and reference voltage output terminals N0-N4 of resistor voltage divider 1. In FIG. 4, the number of the comparator corresponds to the level of an analogue input voltage signal. For example, the input terminals 7-10 of the fourteenth comparator #13 are connected to reference voltage output nodes N3, N4, N4, and N4, respectively, of resistor voltage divider 1. Reference voltage output nodes N0-N4 are connected to input nodes 7-10 so that the output thereof is decreased by one level as the number of the comparator descends. The operation will be explained hereinbelow.
The operation of the comparator of FIG. 3 will be first explained. This comparator operates in two stages.
In the first stage, switches S0-S4 initially establish the connection states of FIG. 3. The switching of these switches are carried out in response to a clock signal from a clock signal applying means not shown. This clock signal determines the sampling rate. Switches S0-S3 connect one nodes of coupling capacitors C0-C3 to analogue voltage applying terminal 6. Switch S4 connects the input of inverting amplifier 11 to bias voltage applying terminal 12. Bias voltage applying terminal 12 is generally supplied with an appropriate voltage V.sub.B that makes inverting amplifier 11 most sensitive.
When the analogue input voltage applied to terminal 6 is Vin, and the capacitance of coupling capacitors C0-C3 is C, charge Q expressed by: EQU Q=C.multidot.(V.sub.B -Vin ). . . (1)
is applied to each of coupling capacitors C0-C3. In other words, charge of 4.multidot.Q is stored in the input terminal of inverting amplifier 11.
This operation is followed by the operation of the second stage. At the second stage, switches S0-S3 connect reference voltage applying nodes 7-10 to one node of respective coupling capacitors C0-C3 in response to a clock signal. Switch S4 is turned off.
This off state of switch S4 causes the charge of 4.multidot.Q stored in the input of inverting amplifier 11 at the first gate to be held also at the second stage.
Because switches S0-S4 have their connection terminal switched from analogue voltage applying terminal 6 to respective reference voltage applying nodes 7-10, the voltage in the input of inverting amplifier 11 changes in response to the applied reference voltage. If the reference voltages applied to each of reference voltage applying nodes 7-10 are V7-V10, and the voltage in the input of inverting amplifier 11 is Va, charge Q' at the input of inverting amplifier 11 is: ##EQU1## Because switch S4 is off, Q'=4.multidot.Q is obtained according to the principle of conservation of charges to provide the following equation from equations (1) and (2): ##EQU2## From equation (3), the following equation is obtained: ##EQU3## The reference voltages Vj applied to comparators are different in each comparator. For example, the comparator #14 receives reference voltages Vj of Vref, Vref, Vref, and 3.multidot.Vref/4. Hence, EQU Va-V.sub.B =3.multidot.(Vref/4)+(3/4.multidot.4) Vref-Vin =15.multidot.Vref/16-Vin
is obtained for comparator #14. The output nodes N0-N4 of resistor voltage divider 1 are connected to comparator input nodes 7-10 so that the total value of the reference voltages decreases by Vref/4 as the number of the comparator descends by 1. Therefore, it can be understood from the table of FIG. 4 that the voltage shift .DELTA.Vj from bias voltage V.sub.B in the input of inverting amplifier 11 is generally expressed as: EQU .DELTA.Vj=((j+1/16).multidot.Vref-Vin . . . (5)
where j is the comparator number. This voltage shift .DELTA.Vj from bias voltage V.sub.B is inverted and amplified by inverting amplifier 11 to be provided as the comparison result. The comparison results from comparator group 2 are applied to encoder 3.
Now, a case is considered where analogue input voltage Vin is between 2.multidot.Vref/16 and 3.multidot.Vref/16. At this time, inverting amplifiers 11 of comparators #2-#14 all provide 0, and inverting amplifiers 11 of comparators #1 and #0 provide 1. Each NAND gate of AND gate array receives the outputs of the adjacent comparators. Therefore, only the output of NAND gate G12 that receives the outputs of inverting amplifiers 11 of comparators #2 and #1 is 0. The comparator which provides a changing output in the output series in the comparator group can be detected, and the level of analogue input voltage Vin is detected to be at a level between the levels of comparators #1 and #2. Therefore, the output from AND gate array 3a (inverters G30-G31 and gate G115) is &lt;15;0&gt;=(00 . . . 0100), to provide a 4-bit data of (0010) from ROM 3b. Thus, a 4-bit digital signal for analogue input voltage Vin in 16 division levels is obtained.
The A/D converter of FIGS. 1 through 3 has a total resolution of four bits by generating four levels with resistor voltage divider 1 (resolution: equivalent to 2 bits) and further generating four levels with coupling capacitors C0-C3 (resolution: equivalent to 2 bits).
In accordance with the above manner, a reference voltage of m bits is generated by a resistor voltage divider (2.sup.m levels) and further voltage-dividing of n bits is carried out by coupling capacitors (2.sup.2 levels), whereby the number of distinguishable levels of the A/D converter is 2.sup.m+n to result in a resolution of (m +n) bits for the A/D converter. In this case, 2.sup.m resistors are necessary in the resistor voltage divider circuit. The total number of coupling capacitors required is 2.sup.n per comparator.
The implementation of an A/D converter having a resolution of (m +n) bits according to the conventional method requires 2.sup.m resistors, and 2.sup.n coupling capacitors per comparator. This means that there is a problem of exponential increase in the number of necessary elements in proportion to the increase of bits of the resolution of the A/D converter.
It was not possible to constitute an A/D converter of high resolution with a small number of elements, resulting in increase in size and cost of the A/D converter.